1. Field of the Invention
The present invention relates to a semiconductor memory device and an information processing system including the same, and more particularly relates to a semiconductor memory device having a plurality of memory circuit units operable independently of each other and an information processing system including the semiconductor memory device. The present invention also relates to a controller that controls the semiconductor memory device.
2. Description of Related Art
Many DRAMs (Dynamic Random Access Memories) as representative semiconductor memory devices have their internal portions divided into plural banks in order to enable parallel operations (see Japanese Patent Application Laid-open No. H11-66841). A controller connected to the DRAMs can individually issue a command to each bank, and when a certain bank is performing a read operation or a write operation, the controller can issue commands to another bank. As a result, banks can perform parallel operations, thereby increasing utilization efficiency of a data bus connected between the DRAMs and the controller.
However, because these bank share a data input/output terminal, read data cannot be output from another bank during a period when read data is being output from a certain bank. Therefore, even when a part of bits of read data output from a certain bank is unnecessary for the controller, read data cannot be output from another bank until when a series of burst output are finished.
In a so-called multibit product, a part of bits of read data is not necessary in many cases. For example, when a DRAM has 32 bits for I/O (input and output) data, a controller requires only 16-bit data in many cases. In this case, the rest of 16 bits are invalidated by the controller. Frequent occurrence of such situations lowers utilization efficiency of a data bus, resulting in a problem that an effective data transfer rate is decreased.
FIG. 9 is a timing chart for explaining this problem.
FIG. 9 is an example of an operation of a DDR synchronous DRAM in which I/O data has 32 bits (DQ0 to DQ31), a burst length is 4 (BL=4), and a CAS latency is (CL=5). Meshed data is necessary data, and unmeshed data is unnecessary data. In this example, because the BL is 4, read commands (A, B, C, and D) can be input at every two clock cycles.
At one-time access, 128-bit (=32×4) data is output from such a DRAM. In the example shown in FIG. 9, either 64-bit data output from DQ0 to DQ15 or 64-bit data output from DQ16 to DQ31 is necessary data, and rest of the data is not necessary. In this case, because only a half of the output data is necessary, the effective data transfer rate decreases to a half.
While a problem in the read operation has been explained with reference to FIG. 9, this problem also occurs in a write operation.
As described above, according to a conventional semiconductor memory device, when a part of read data or write data is unnecessary data, its effective data transfer rate decreases. This kind of problem occurs noticeably in multibit products having a large number of I/O bits.